The present invention relates to a semiconductor device, particularly to a semiconductor device having a multi-layer buried wiring structure.
Attendant on rises in the degree of miniaturization and the degree of integration of semiconductor devicees, the delay of electrical signals arising from the time constant of wiring becomes a serious problem. Therefore, in multi-layer wiring structures of the semiconductor devicees, copper (Cu) wirings higher in conductivity have come to be introduced in place of aluminum-based alloy wirings. Unlike the metallic materials, such as Al, used for the multi-layer wiring structures in the past, Cu is difficult to pattern by dry etching. Therefore, to the formation of a Cu wiring, the so-called Damascene process has been applied in which a wiring trench is first formed in a layer insulation film, and then the wiring trench is filled up with Cu to thereby form a wiring pattern. Particularly, the dual Damascene process in which a wiring trench formed in a layer insulation film and a contact hole formed at a bottom portion of the wiring trench are simultaneously filled up with Cu is effective for reducing the number of steps (see Japanese Patent Laid-Open No. Hei 11-45887).
In addition, in a semiconductor device advanced in the degree of integration, an increase in wiring capacity leads to a lowering in the operating speed of the semiconductor device, and, therefore, it may be indispensable to lower the dielectric constant of the layer insulation film so as to suppress the increase in the wiring capacity.
FIG. 8 shows a sectional diagram of a semiconductor device having a multi-layer buried wiring structure obtained by application of the dual Damascene process. The semiconductor device shown in the figure has a configuration in which a local wiring layer 0 is provided on a semiconductor substrate (omitted in the figure) formed with semiconductor devices such as MOS transistor, with an under layer insulation film 1 of silicon oxide therebetween, and a first wiring layer 10-1, a second wiring layer 10-2 and so on having buried wirings are laminated on the local wiring layer 0.
Of the above-mentioned layers, the local wiring layer 0 includes a local wiring 6a formed by sequentially laminating a carbon-containing silicon oxide (SiOC) film 2 and a hard mask layer 3 of silicon oxide (SiO2) on the under layer insulation film 1 to form a layer insulation film, and a trench pattern “a” formed in the layer insulation film is filled up with a copper (Cu) film 5, with a barrier metal 4 therebetween.
In addition, the first wiring layer 10-1 laminated on the local wiring layer 0 is formed in a layer insulation film obtained by laminating an anti-oxidation film 11 of silicon carbide (SiC), a low-dielectric-constant film 12, and a hard mask layer 23 of silicon oxide (SiO2) in this order. The layer insulation film 11 to 13 is provided with wiring trenches “a” and a contact hole b formed to extend from the lower surface of the wiring trench “a” so as to reach the local wiring 6a, and the inside of the wiring trenches “a” and the contact hole b is filled up with a conductive film 15 of copper (Cu) or the like, with a barrier metal 14 therebetween, to form buried wirings 16a and a via 16b connected thereto.
Then, the second wiring layer 10-2, the third wiring layer 10-3 and so on configured in roughly the same manner as the first wiring layer 10-1 are sequentially laminated on the first wiring layer 10-1, to constitute a multi-layer buried wiring structure. The buried wiring 16a in each of these wiring layers 10-2, 10-3, . . . is in connection with the buried wiring 16a of the underlying layer through the via 16b. 
Here, examples of the material constituting the low-dielectric-constant film 12 constituting the most part of the multi-layer buried wiring structure as above include not only the fluorine-containing silicon oxide (FSG) having a dielectric constant of about 3.5 which has been used comparatively frequently and successfully in the past but also organic polymer based materials represented by polyaryl ether (PAE), and materials having a dielectric constant of around 2.7 such as SiOC based materials represented by hydrogensilsesquioxane (HSQ) and methylsilsesquioxane (MSQ). Furthermore, in recent years, application of low-dielectric-constant materials obtained by making these materials porous to obtain a dielectric constant of around 2.2 has been tried.
However, in the case of further lowering the dielectric constant of the low-dielectric-constant film 12 in the above-mentioned multi-layer buried wiring structure, there arise other serious technical problems such as degradation of the mechanical strength of the wiring layers. In other words, the dielectric constant and the mechanical strength of a dielectric material are usually in a trade-off relationship. Therefore, a lowering in the mechanical strength of the low-dielectric-constant film 12 constituting the most part of the wiring layers leads to a degradation of the mechanical strength of the wiring layers.
As an index of mechanical strength, hardness and elastic modulus are used. For example, while the elastic modulus of a silicon oxide film having a dielectric constant of about 4.2 is not less than 70 GPa, the elastic modulus of fluorine-containing silicon oxide (FSG) having a dielectric constant of about 3.5 which has been introduced in the 130 nm generation is as low as around 60 GPa, and, further, the elastic modulus of carbon-containing silicon oxides film (SiOC) having a dielectric constant of around 3 which have started to be introduced in the 90 nm generation is as low as about 10 GPa. Furthermore, it has been found that the porous low-dielectric-constant films having a dielectric constant of 2.5 or below the introduction of which has been investigated for the 45 nm generation and later generations show an elastic modulus as low as 5 GPa or below.
The lowering of the mechanical strength of the wiring layers as above-mentioned would cause film exfoliation or deformation in the manufacturing process of the multi-layer buried wiring structure shown in FIG. 8. Specifically, in the case of forming the buried wirings 16a and the via 16b in each of the wiring layers 10-1, 10-2, . . . , the formation of the Cu film in the state of filling up the wiring trenches “a” and the contact hole b is followed by the step of removing the surplus Cu film and surplus barrier metal film on the layer insulation film 11 to 13 by Chemical Mechanical Polishing (CMP). In the CMP step, a polishing pressure is exerted on the low-dielectric-constant film 12 which is poor in mechanical strength, so that the above-mentioned film exfoliation or deformation is liable to occur. Besides, such a trouble becomes more liable to occur as the number of wiring layers in the multi-layer wiring structure increases.
For example, in the case where a porous carbon-containing silicon oxide (SiOC) film having a dielectric constant of 2.2 and an elastic modulus of 4 GPa was used as the low-dielectric-constant film 12 in the manufacture of the multi-layer buried wiring structure shown in FIG. 8, the layers up to the first wiring layer 10-1 could be formed successfully, but film exfoliation of the layer insulation film occurred in the process of forming the second wiring layer 10-2. To be more specific, in the CMP step in the process of forming the second wiring layer 10-2, film exfoliation occurred at a low frequency in the vicinity of the low-dielectric-constant film 12 composed of porous carbon-containing silicon oxide (SiOC), at specific wiring layout locations.
In addition, in the CMP step in the process of forming the third wiring layer 10-3, further conspicuous exfoliation of the layer insulation film occurred. The film exfoliation occurred in the vicinity of the low-dielectric-constant film 12 constituting the second wiring layer 10-2 and in the vicinity of the low-dielectric-constant film 12 constituting the first wiring layer 10-1, at a frequency of about 5 times the frequency of film exfoliation generated in the process of forming the second wiring layer 10-2.
Similarly, in the CMP step in the process of forming the fourth wiring layer 10-4, a serious degree of exfoliation of the layer insulation film occurred. The film exfoliation occurred in the vicinity of the low-dielectric-constant film 12 constituting the fourth wiring layer 10-4, in the vicinity of the low-dielectric-constant film 12 constituting the third wiring layer 10-3 and in the vicinity of the low-dielectric-constant film 12 constituting the second wiring layer 10-2, at a frequency of about 25 times that of film exfoliation generated in the process of forming the second wiring layer 10-2.
In addition, if the wiring layers up to the uppermost wiring layer could be successfully formed without generation of film exfoliation, there would still remain the problem that the semiconductor device is liable to be broken at the time of packaging the semiconductor chip having the multi-layer buried wiring structure.
Thus, the following has been found. On one hand, in the case of composing the low-dielectric-constant film as the main component of the layer insulation film by use of a non-porous carbon-containing silicon oxide (SiOC) film having a dielectric constant of about 2.9 and an elastic modulus of about 10 GPa, there was no problem of film exfoliation in the manufacturing process. On the other hand, in the case where the low-dielectric-constant film as the main component of the layer insulation film is further lowered in dielectric constant and a porous carbon-containing silicon oxide (SiOC) film having a dielectric constant of about 2.2 and an elastic modulus of about 4 GPa is used, an obvious trouble occurs due to the lowering of mechanical strength.
In addition, it has been recognized that the generation of this trouble depends on the constitution of the laminate structure and the wiring layout. Specifically, it has been found out that the production of the low-dielectric-constant film as the main component of the layer insulation film by laminating a porous carbon-containing silicon oxide (SiOC) film having a dielectric constant of 2.2 and an elastic modulus of about 4 GPa accelerates the generation of this trouble. This implies that not only the elastic modulus of the low-dielectric-constant film but also the proportion of the low-elastic-modulus low-dielectric-constant film in a specified multi-layer wiring region is important.
As a method for improving the above-mentioned trouble attendant on the progress of the lowering in the dielectric constant of the layer insulation film, a method of lowering the pressure in the CMP process has been proposed (see S. Kondo et Al., “Low-pressure CMP for reliable porous low-k/Cu integration,” IITC, (USA), 2003, pp. 86 to 88).
In addition to the above, a method in which a low-dielectric-constant film having a comparatively higher elastic modulus is applied to the layers formed with the via (i.e., the portion between the wiring layers) and a low-dielectric-constant film having a sufficiently lower dielectric constant (and, hence, having a comparatively lower elastic modulus) is applied only to the layers formed with the buried wirings has also been proposed (see S. Nakai et Al., “A 65 nm CMOS Technology with a High-Performance and Low-Leakage Transistor, a 0.55 μm2 6T-SRAM Cell and Robust Hybrid-ULK/Cu Interconnects for Mobile Multimedia Applications,” IEEE, (USA), 2003, pp. 285 to 288).